1. Field of the Invention
The present invention generally relates to data communication and, more particularly, to sampling data in communication receivers.
2. Related Art
In many high speed communication systems using serial non-return-to-zero (NRZ) modulated waveforms (e.g., USB 3.0, PCI Express, SATA/SAS, and optical transmission), information on the transmitting clock used to transmit data is embedded in the transmitted data itself. Transceivers receiving such waveforms use local clocks that are asynchronous to the transmitting clock. Because the transmitting and receiving clocks are asynchronous, clock and data recovery circuitry are often used in the transceiver to extract information on the transmitting clock from the received data. Subsequently, the extracted transmitted clock is used to recover the data from the received data.
Conventionally, clock and data recovery circuitry are implemented in the analog domain using analog PLLs that may include a phase detector, a loop filter, and a VCO (voltage controlled oscillator). However, analog PLLs suffer from large die size, high power consumption, and limitations such as injection locking when there are multiple VCOs. Furthermore, because areas of loop filters are inversely proportional to the loop bandwidth, PLL die areas will grow as increasingly smaller loop bandwidth is required to track higher speed clock embedded in the received data.
Alternatively, clock and data recovery circuitry may be implemented in digital PLLs. A digital PLL may include a digital phase detector, a digital loop filter, and an analog interpolator to replace the phase detector, the loop filter, and the VCO, respectively, of an analog PLL. Digital PLLs using digital loop filters have die areas that are significantly smaller than analog PLLs. Digital PLLs also have die areas that are substantially independent of loop bandwidth. However, like all feedback loops, digital PLLs suffer from limitations in tracking speed. They also incur delays in achieving timing lock that is inversely proportional to the loop bandwidth. In addition, digital PLLs are susceptible to ISI (inter-symbol interference). Accordingly, there is a need for an improved clock and data recovery implementation that achieves fast tracking, has a small footprint, is immune to ISI, and consumes low power.